Methods and metrics for reliability assessment

Naviner, Lirida Alves de Barros; Naviner, Jean-François; Franco, Denis Teixeira; Vasconcelos, Maï Correia de


This paper deals with digital VLSI design aspects related to reliability. The focus is on the problem of reliability evaluation in combinational logic circuits.We present some methods for this evaluation that can be easily integrated in a tradidional design flow. Also we describe suitable metrics for performance estimation of concurrent error detection schemes.

Show full item record


Files in this item

This item appears in the following Collection(s)


  • C3 - Artigos Publicados em Periódicos